High Performance, Low Cost…

What Are FPGA’s ?

FPGA’s, or field-programmable gate arrays, are arrays of programmable logic elements that can be used to build complex instruments. Programmed in a hardware description language such as VHDL, or Verilog, FPGA’s allow a very large number of processes to execute in parallel at very high speed. Software provided by the major FPGA vendors (such as Altera, Xilinx and others) allow complex logic circuits to be created by wiring together the outputs/inputs of inter-connected modules that can either be drawn from extensive libraries of standard logic gates, flip flops and shift registers or alternatively from user-coded logic. Although the learning curve to use these devices is quite steep, they offer many attractive benefits.
Here is a very simple Verilog module named div5000.v that divides an input clock (clk) signal by 5000, generating an output clock (q) of a lower frequency. To apply a divisor of n to the input clock the constant in this module is simply changed to (n/2)-1.

Building a New Project on an FPGA Development Board

The DE0-Nano is a low cost FPGA board manufactured by the Taiwanese company Terasic. Here, we explain the steps required to build a very simple FPGA project to run on this platform using the afore-mentioned file div5000.v. This project is not particularly useful, but it is conceptually simple and nicely illustrates the process by which an FPGA can be used to construct programmable logic.

The DE0-Nano has an on-board 50MHz clock. We will create two instances of our divide-by-5,000 module and connect the output of the first to the input of the second in order to generate a divide-by-25,000,000 signal with a 50% duty cycle. Then, by feeding in the 50 MHz clock at the input pin, the output will be a 2 Hz square wave. This signal will be connected to one of the DE0-Nano’s on-board LED’s to provide a visual indication that the project is functioning correctly.


1. Create a folder called Clock_Divider and save the file div5000.v into that folder
2. Launch Quartus II 15.0 web edition and select new Project Wizard (the software is available from the Altera website)
3. Set the working directory to point to the Clock_Divider folder, set the project name to try1 and set the top level design entity to try1
4. Click through to Family & Device Settings and choose a Cyclone IV E device - on the DE0-Nano this is an EP4CE22F17C6, then click through to Finish
5. Navigate to File->Open.. and open div5000.v
6. Navigate to File->Create/Update->Create Symbol Files for Current file
7. Choose menu option File->New… and choose Block Diagram/ Schematic File - a worksheet named Block1.bdf will open
8. Right mouse click in the bdf file and insert the symbol div5000 onto the worksheet (the symbol will be located in the Project folder)
9. Repeat to place a second div5000 symbol onto the worksheet
10. Right mouse click again in the .bdf file and insert an input pin (located in the Pin folder under Primitives in Quartus libraries)
11. Right mouse click again in the .bdf file and insert an output pin
12. Connect the output of the first div5000 block to the input of the second and then wire up the input pin and output pins as shown in the diagram below
13. Navigate to the File menu and save the .dbf file as try1.bdf
Stacks Image 5043
Here one sees the two div5000 blocks placed on the worksheet. On the left hand side of each block is its clock input pin, and on the right hand side its q output pin. The output of the first block feeds the input of the second.

Input and output pins to/from the series connected blocks are wired to physical pins on the FPGA by defining pin assignments in a .qsf file, as described in step 15 below.
14. Navigate to Menu Processing->Start->Start Analysis and Elaboration. After processing has completed you should have no errors
15. Next go to Menu Assignments->Pin Planner, then click in the location field for each pin in the design and assign the pin e.g. to the clk pin type R8, then enter - the field changes to PIN_R8. For the q pin type A15, then enter - the field changes to PIN_A15. (The DE0-Nano manual lists pin assignments for the board’s IDC connectors, master 50MHz CLK pin and the on-board LED’s - e.g. the 50 MHz clock is R8, LED0 is A15, LED1 is A13, LED2 is B13, LED3 is A11, PB input is J15 etc)
16. Navigate to Menu Processing->Start Compilation (After completion - in a minute or so - there should be no errors)
17. Navigate to Menu Tools->Programmer, then add the project's .sof file from the output files folder
18. Finally press the Start button and the design file should be loaded into the FPGA, then run. LED0 show now be blinking at 2Hz

Custom P1V Builds - Using the P1V Toolbox

Parallax have made their Verilog code available in the public domain so that users can emulate their P8X32 Propeller chip on an FPGA platform of their choice. This code suite is referred to as P1V.

The P1V concept can be taken further using a PC program that allows one to build custom implementations of P1V. P1V_Toolbox has been developed and generously made available to the wider community by one of the Parallax Forums regular contributors, Brian Dennis (ozpropdev). P1V_Toolbox modifies the original Parallax-supplied Verilog code according to a set of user commands - see below for an example.

When the target FPGA’s resources allow, custom P1V builds can expand the Propeller’s hub memory, and add many additional I/O pins via the use of PORTS B, C and D. Additionally, the clock frequency of the emulated Propeller can be boosted beyond the standard 80 MHz.

While the silicon (i.e real) P8X32 Propeller chip can only access PORT A (32 I/O pins), these FPGA emulations can greatly expand the capabilities of the Propeller - for example if one wanted to add significant amounts of external memory - to do so would otherwise be problematic having just PORTA as it would rapidly consume precious I/O pins. By adding PORTS A, B and C the user potentially has access to an additional 96 I/O pins !

As an example, to build a 7 COG P1V implementation with 48k of HUB RAM and PORT B activated to run on a DE0-Nano FPGA board, we issue the following P1V_Toolbox commands :

new demo
target nano
cogs 7
video -
ctr 2
portb +
hub 48
romsize 4
char -
rom myrom

(Here, the commands char - and romsize 4 remove the Propeller’s character ROM and sin/log tables, freeing up space to expand the normal 32k of HUB RAM). In the above example, an 8 COG P1V is possible by reducing the HUB RAM to 40k.

Next Step - P8X32 Emulation on a Helix-4 Module

The Helix-4 module (formerly made by the Australian company Thin Layer Embedded and seen in the photo below) is populated with a 4CE22 FPGA, as well as having 256k x 16 bits of SRAM on-board. Here, this easily soldered module has been integrated onto a motherboard with an FT232R. This will allow us to access the Propeller emulation via a USB connection, while an on-board 24LC256 EEPROM provides a means to store user programs.

Accessing all of the on-board hardware here requires a custom P1V build with PORT B added, as illustrated in the aforementioned P1V_Toolbox example.

The resulting Propeller emulation provides access to an extra 512k of SRAM compared to the actual P8X32A chip, while numerous I/O pins are brought out to SIL connectors at J7, J8 and J9. The result is a flexible platform that can either be used as a Propeller or as an FPGA breakout for various high-end instrument projects.

Project Build Instructions

In the following instructions the project file generated by the P1V_Toolbox is assumed to be named top.qpf. On my PC this resides in the folder P8X32_Helix4_WithPortB_8COGS_4CE22_120MHz. The emulation described here provides 8 COGS + PORTB and runs at 120 MHz on the 4CE22 FPGA. The latter is the same FPGA chip as used on the Terasic DE0-Nano board. The only difference is the speed grade – on the DE-0 Nano the part is a -6 grade while the Helix-4 uses a slower -8 part.

1) Launch Quartus 15.0, and open top.qpf. Important note - a separate file named top.qsf is required containing important pin assignments for the project, as discussed later.

2) Click Start Compilation.. A full compile will take ~ 8-10 minutes.

3) Compilation generates a file named top.sof.

4) Prior to the next step, connect an Altera blaster programmer to a USB port on the PC, and the 10 pin ribbon cable from the blaster to the JTAG header on the right hand side of the Helix-4 breakout board. Pin 1 is in the top left corner of the IDC header (J1).

5) Next, drag and drop the top.sof file onto the .sof to .jic converter .bat file. A .jic file will be generated and the programmer will load the .jic file into the EPCS chip on-board the Helix-4 module. Once this process has completed, the Helix-4 will emulate a Propeller P8X32 after the power is cycled.

The Propeller emulation here extends the capabilities of the real P8X32 chip to interact with two bi-directional 32 bit ports, PORTA and PORTB. PA31 and PA30 are dedicated for the FT232R serial link, while PA29 and PA28 are connected to the SCL and SDA pins on the EEPROM.

In the implementation described here, the Helix-4 module’s on-board SRAM connects to the Propeller emulation as follows :

SRAM interface

The SRAM address bus A17…0 maps to Propeller pins PB17..0
The SRAM data bus DQ15…0 maps to Propeller pins PA15..0

SRAM control pins

The design makes use of 5 control signals; these are connected to Propeller pins PB22..18. Details of these connections are as follows :

OE = PB18
CE = PB19
WE = PB20
LB = PB21
UB = PB22

Spare I/O pins

After implementing the SRAM, FT232R and EEPROM interfaces, there are 20 uncommitted Propeller I/O lines - PA27..16 and PB31..23. These are brought out to connectors on the Helix-4 motherboard. The many additional spare FPGA pins are also routed to these connectors. In the following section we will describe how these latter pins can be accessed in a user’s project. While the discussion here relates to specifically to the Helix-4 module, the general concepts would be the same on any target FPGA board.

The .qsf pin definition file

As is normal practice, the Quartus design software makes use of a separate pin definition file top.qsf to define which physical FPGA pins map to which Propeller pins. To do this one must consult the target FPGA board’s hardware manual.

A test program that exercises the SRAM interface and has 3 COGS running simultaneously is 3COGS_120MHz_SRAM_Final.spin. When this program is loaded the 3 LED’s on the motherboard light up, indicating that 3 COG’s are active.

In the following section, we shall go through the exercise of adding a separate verilog module to a P1V build created by ozpropdev’s Toolbox (thanks to Brian for helping me to get this working !).

Creating a Quartus 15 Project with a Custom P1V Build and Additional Verilog (.v) Module(s)

Frequently, the user’s FPGA board will have uncommitted I/O pins over and above those that need to be assigned to Propeller pins after doing a custom P1V build. These extra pins can still be used in a project and this will typically be done by writing custom Verilog code to access them. Here is a procedure illustrating how to link a custom P1V_Toolbox build with code that resides in a verilog module (.v).

1] First, build your desired flavour of P1V using the P1V_toolbox software developed by ozpropdev. Prior to issuing the build command, enter “top prop” so that a text design file named prop.tdf will be generated.

2] Create a new project named “top” in Quartus, and set the working directory to the folder containing your P1V files.

3] Set the device to whatever target FPGA you are using.

4] Under Settings..., set the verilog compiler to SystemVerilog, and
in Compiler Settings – Advanced settings (synthesis) – set block design naming to “Quartus II”.

5] Open prop.tdf, and then choose File – Create/Update – Create Symbol Files for current file – this will create a schematic block for the P1V named prop.bsf.

6] Next, navigate to File – New – Block Design File, and save this as top.bdf.

7] Place prop.bsf onto the top.bdf sheet. This is done by right-clicking on the worksheet and selecting prop.bsf file under the project folder.

If all you require is a bare P1V, you can now wire up the pins using a naming scheme compatible with your top.qsf. The file top.qsf assigns named P1V pins to actual FPGA pins and this will depend on the exact hardware configuration you are using.

8] Let's assume that you now have an additional verilog module that you would like to connect to the P1V. If so, open the file (say mymodule.v) and create a block symbol file for the module.

9] Right-click on top.bdf and add mymodule.bsf. At this point all interconnections between the P1V and mymodule blocks should be wired up. Then, all inputs and outputs need to be connected (see point 7 above regarding the .qsf file).

10] In the project navigator, select top.bdf as the top entity. Be sure to Import your pin assignments from top.qsf.

11] Your project is now ready to go, so navigate to Start Compilation.

If during compilation you see the error

Error (12006) : Node instance “inst2” instantiates undefined entity “mymodule”, then
go to the project navigator  - Files , and right click to add the file to the project.

Once compilation is finished, the file top.sof will have been generated and this may be used to program the FPGA, as described earlier.

The image below shows the appearance of the top.bdf sheet after following the above procedure.
Stacks Image 5214


Here, module prop was created via a P1V build that included use of PORTB. Prop’s I/O pins are internally designated IO[31..0] and IOB[31..0]. Module pshift was generated from separate Verilog code in the form of a text file - pshift.v. On receipt of an external trigger signal, this module generates a sequence of bit patterns on 4 FPGA pins CLKP[3..0]. In addition it toggles an LED to indicate activity.

A Practical Application in 2D Imaging

In the image at right, the EP1C3 FPGA board in an area-array 2D imaging system has been replaced by a custom P1V build running on the Helix-4 platform, as just described.

Instead of needing separate, dedicated SRAM chips to store a captured image, this implementation uses SRAM on-board the Helix-4 module, now accessed by PASM code running on the Propeller.

All CCD clocking operations are now also handled by the Propeller, making the spectrometer much easier to program and modify.